Synchronous dynamic random access memory (SDRAM) devices are gradually replacing asynchronous DRAM devices as a preferred memory architecture because of their wider bandwidth of operation and because they can be more efficiently controlled. Unfortunately, many SDRAM devices require considerably more power than DRAM devices, even when operating in standby mode. Thus, the use of SDRAM devices in battery operated circuits may be limited.
As will be understood by those skilled in the art, the amount of power consumed by an SDRAM device can be reduced by using a clock enable signal CKE to induce the standby mode. However, the use of a clock enable signal CKE may result in a delay equivalent to one clock cycle and may require the use of additional I/O pins. Thus, notwithstanding the advantages of using SDRAM devices instead of DRAM devices, there continues to be a need for SDRAM devices having reduced power consumption requirements.